This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS ...

Often, when you are designing with high-speed ECL (emitter-coupled logic), you have too little time between clock cycles to implement logic functions using gates between flip‑flops. In these cases, ...

The three main logic families in the 1980s were TTL, ECL, and CMOS. The three main logic families in the 1980s were TTL, ECL, and CMOS. In my previous column, we started our look at logic data sheets ...

Three new ultra-high speed logic devices have been added to the company's ECL Pro logic family—the ever-expanding ECL Pro logic family is said to offer an easy upgrade path from On Semiconductor's ...

This course presents the building blocks and concepts associated with digital electronic networks. The material presented will cover the design requirements necessary to develop successfully ...

The phase-frequency detector (PFD) consists of 2 D-trigger with reset from external circuit, performed in ECL logic and multiplexer, which allow to sw ...

ON Semiconductor has released two new clock distribution ICs. The NB6L56 presents the industry with a more advanced 2:1 signal management solution. Two new clock distribution ICs are available from ON ...

[Matthew] got himself into a real pickle. It all started when he was troubleshooting a broken Hewlett Packard 8007A pulse generator. While trying to desolder one of the integrated circuits, [Matthew] ...