Electronic Design

Enhanced Logic, Clock Management Give FPGAs 500-MHz Internal Speed

Designing high-speed digital systems on FPGA platforms has always been challenging. The large amounts of routing required by SRAM-based FPGAs often limits system performance to well below that ...
EDN

SmartDV’s LPDDR5 IP Clocks 612 MHz in FPGA Functional Test, 1.6 GHz at 28 nm

Outperformed competition by 3× during recent customer evaluation. SmartDV Technologies has confirmed that its LPDDR5 SDRAM controller design intellectual property (IP) achieved a speed of over 600 MHz ...